1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, particularly to a semiconductor integrated circuit device including a phased locked loop (PLL) circuit for receiving a reference clock signal from the outside.
2. Description of the Related Art
PLL circuits are used for the purpose of multiplication, phase lock, clock extraction and the like. PLL circuits are widely used in various types of electronic equipment for the purpose of, for example, generating a high-frequency clock signal from a low-frequency reference clock signal. PLL circuits have a feed back control function for controlling a voltage controlling oscillator. The control is performed depending on a comparison result that is obtained by receiving and amplifying a signal outputted from a quartz oscillator or the like, thus comparing a reference signal obtained by dividing the resultant signal by use of a reference frequency divider with a signal obtained by dividing the frequency of an oscillation signal from a voltage controlling oscillator (see Japanese Patent Application Laid-open Publication No. 2002-57578, for example). Such PLL circuits make it possible to output a clock signal with a stable frequency for multiplication, phase lock, and clock extraction by using a signal outputted from a quartz oscillator with a stable oscillation frequency as a reference signal.
Generally speaking, in a case where a PLL circuit is included in a semiconductor integrated circuit device, a quartz oscillator or the like for generating a reference frequency signal is mounted, as an exterior attached device, on the exterior of the semiconductor integrated circuit device. In this case, some arrangement position of interconnections between the semiconductor integrated circuit device and the quartz oscillator is likely to allow the interconnections to be influenced by the neighboring interconnections, thereby allowing noise to be superimposed on a signal outputted from the quartz oscillator and to thus go into the semiconductor integrated circuit device. In a case where the PLL circuit receives a signal on which the noise is superimposed, the PLL circuit outputs a clock signal including a lot of jitters.